1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory cells storing data and a sense amplifier circuit amplifying data read out from each memory cell, and particularly relates to a semiconductor memory device in which the memory cells and the sense amplifier circuit are configured using floating body type NMOS transistors.
2. Description of Related Art
A structure using an SOI (Silicon on Insulator) substrate has been known in order to achieve high speed operation and low consumption current in a semiconductor memory device such as a DRAM (Dynamic Random Memory). Generally, a MOS transistor using the SOI substrate operates as a so-called floating body type MOS transistor in which a body formed in a region between a source and a drain on an insulating film is in a floating state. For example, considering an operation of an N-type MOS transistor (NMOS transistor) in which a floating body is formed, a phenomenon occurs in which a large number of electron-hole pairs are generated due to impact ionization and holes as minority carriers are accumulated in the body over time. Such a phenomenon causes various characteristic deteriorations in the MOS transistors. For example, parasitic bipolar effect occurs, a threshold voltage decreases, or a kink appears in voltage current characteristics. As measures against these characteristic deteriorations in the case of employing the SOI substrate, various methods have been proposed in, for example, Patent References 1 to 8 and a Non-Patent Reference 1.    Patent Reference 1: Japanese Patent Application Laid-open No. 2006-324683    Patent Reference 2: Japanese Patent Application Laid-open No. 2006-173640    Patent Reference 3: Japanese Patent Application Laid-open No. 2003-7856    Patent Reference 4: Japanese Published Japanese Translation No. 2003-503856    Patent Reference 5: Japanese Patent Application Laid-open No. H11-284146    Patent Reference 6: Japanese Patent Application Laid-open No. H11-284137    Patent Reference 7: Japanese Patent Application Laid-open No. H9-246483    Patent Reference 8: Japanese Patent Application Laid-open No. H6-21400    Non-Patent Reference 1: J. Barth, et al., “A 500 MHz Random Cycle 1.5 ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier”, ISSCC Digest of Technical Papers, pp. 486-487, February 2007
The above-mentioned conventionally proposed methods include a technique to couple a fixed voltage to the body of a MOS transistor using the SOI substrate (Patent References 1 and 2), and a technique to form a conductive layer for supplying a fixed voltage (Patent References 3 and 4). Further, the above methods include a technique to separate a MOS transistor using the SOI substrate by forming a field shield layer thereon and to fix the potential of the body by locally controlling an electric field (Patent References 5 and 6). Further, the methods include a technique to allow holes accumulated in the body to escape by a control called “body refresh” (Patent Reference 7). Further, the above methods include a technique to form a memory cell using a P-type MOS transistor and to use electrons as majority carriers which are prone to be extracted from the body (Patent Reference 8). Further, the methods include a technique to precharge a bit line to a predetermined power supply voltage for a memory cell including a MOS transistor using the SOI substrate (Non-Patent Reference 1).
However, when employing the above conventional methods, there is a problem that an increase in chip area or in cost is inevitable. For example, a region for forming a complex structure and lines is required on and around the MOS transistor on the SOI substrate, or it is required to add a special process step in manufacturing process.